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TECHNICAL INSIGHT • HIGH-SPEED INTERCONNECT
From 90GHz to 110GHz+, next-generation PCB via design is pushing the physical limits of copper interconnects. mSAP, laser microvias, and SLP are building the interconnect foundation for 800G/1.6T AI networks.
Apex Group Editorial Team|June 16, 2026|8 min read
⚡ KEY TAKEAWAY
Traditional PCB technology can reach ~110GHz bandwidth through material upgrades and structural optimization. SLP (Substrate-Like PCB) with mSAP and laser microvias delivers even higher bandwidth, lower crosstalk, and superior routing density — making it the most promising copper interconnect platform for the 448Gbps era.
Over the past few years, the rapid advancement of large-scale AI models has continuously redefined our understanding of compute power. From 112G to 224G, and now the industry sprint toward 448Gbps, high-speed interconnect technology is evolving at an unprecedented pace.
But here's the reality most system architects are waking up to: when signal frequencies cross the 100GHz threshold, the real performance bottleneck is no longer the silicon. It's the PCB vias, Fan-Out structures, connectors, and other passive channel elements that stand between your SerDes and the outside world.
At Apex, we sit at the intersection of copper and optics. While our core business spans optical transceivers (1.6T down to 1G), active optical cables (AOC), WDM multiplexers, and optical amplifiers, we believe deeply in understanding the full signal path. Because every optical link starts and ends with an electrical interface. If the copper channel fails at 100GHz, the optics don't matter.
This analysis draws on recent industry research examining the design, simulation, fabrication, and measurement of via structures targeting 448Gbps PAM4 and PAM6 signaling. The findings have direct implications for AI servers, data center switches, and next-generation 800G/1.6T network equipment.
Whether the industry standardizes on PAM4 or explores PAM6 for 448Gbps, the Nyquist frequencies are sobering:
| MODULATION | NYQUIST FREQUENCY | IMPLICATION |
| PAM4 | ~112 GHz | Strictest bandwidth requirement |
| PAM6 | ~90 GHz | Lower bandwidth, higher SNR demand |
Either way, traditional PCB channels have officially entered the 100GHz design era. The bottleneck is no longer the SerDes IP — it's the connectors, vias, Fan-Out structures, and PCB dielectric materials.
Research based on 224Gbps via structures reveals that via bandwidth is dominated by a handful of physical parameters. A Design of Experiments (DOE) analysis identifies the top three:
00001. Stub Length — Unused via barrel sections create resonant stubs that devastate high-frequency performance. Back-drilling is essential.
00002. Pad Annular Width — Excess pad capacitance loads the signal path, pulling down the impedance and bandwidth.
00003. Drill Diameter — Larger barrels mean higher capacitance to surrounding planes, limiting the achievable bandwidth ceiling.
As dielectric constant (Dk) decreases, signal propagation velocity increases, high-frequency loss drops, and via bandwidth rises significantly:
| DK VALUE | MATERIAL CLASS | BANDWIDTH POTENTIAL |
| 3.3 | Standard FR-4 / mid-loss | ~90 GHz |
| 3.1 | Mid-loss enhanced | ~95 GHz |
| 2.9 | Low-loss | ~100 GHz |
| 2.7 | Ultra-low-loss | ~110 GHz |
| 2.5 | Extreme low-loss | 110 GHz+ |
Bottom line: 448Gbps PCB designs must adopt ultra-low-loss material systems. Conventional materials simply cannot meet the 112GHz frequency demands.
Two design generations were fabricated and validated:
| DESIGN | PROCESS | DK | MEASURED BANDWIDTH |
| Design I | Mature PCB, optimized drill + back-drill + shield vias | ~3.3 | > 90 GHz |
| Design II | Next-gen PCB, ultra-low-loss materials | ~2.7 | > 110 GHz |
Simulation and measurement showed strong agreement, confirming that traditional PCB technology — when paired with advanced materials and rigorous via optimization — remains viable for 448Gbps copper interconnects.
�� Design implication for optical transceiver engineers: When integrating 448Gbps electrical interfaces into pluggable or on-board optics, the host PCB via design and material selection directly impact link margin. Apex works with customers to ensure the complete electrical-to-optical path meets end-to-end signal integrity targets.
At 100GHz+, crosstalk becomes a first-order design constraint. Research examined both In-Row Crosstalk (between adjacent differential pairs in the same row) and In-Column Crosstalk (between pairs in the same column). The finding: In-Column Crosstalk is significantly worse.
Three mitigation strategies proved effective:
00001. Increase Pair Pitch — Simple but consumes board real estate
00002. Skew Differential Pair Angle — 15°, 30°, and 45° angles all demonstrably reduce crosstalk
00003. Optimize Shield Via Placement — For 110GHz, shield via spacing must be < λ/4.5, with further improvement to < λ/6 to maintain crosstalk below −40 dB
Perhaps the most significant finding: SLP (Substrate-Like PCB) demonstrates overwhelming advantages over traditional PCB.
| METRIC | TRADITIONAL PCB (OPTIMIZED) | SLP (MSAP + LASER MICROVIA) |
| Process | Conventional subtractive etch | mSAP (modified Semi-Additive Process) |
| Line/Space | ~50/50 µm | < 15/15 µm |
| Via Type | Mechanical drill | Laser microvia + stacked via |
| Stub | Requires back-drill | Minimal / eliminated by design |
| Bandwidth | ~110 GHz | > 150 GHz (no resonance observed) |
| Crosstalk | −40 dB (optimized) | < −50 dB across full band |
Even with longer via structures, SLP showed no significant resonance below 150GHz and maintained crosstalk below −50 dB across the entire frequency range — performance that far exceeds even the best conventional PCB implementations.
Because SLP layer counts are inherently limited, future Fan-Out designs will increasingly rely on Layer Transition Vias for true 3D routing:
· ▶Buried vias that jump signal paths between different layers
· ▶Cross-Over Routing for flexible signal path planning
· ▶Higher channel density with lower per-channel loss
This approach is increasingly converging with package substrate design methodologies — a trend that will reshape how we think about the boundary between PCB, interposer, and package.
�� APEX PERSPECTIVE
The 448Gbps transition is not just an electrical engineering challenge — it's a system-level co-design problem spanning PCB materials, via topology, connector selection, and the electrical-to-optical conversion interface. At Apex, our optical transceiver and AOC product roadmap is built with these channel realities in mind. Whether you're architecting a 51.2T data center switch or a next-gen AI training cluster, we're here to ensure your optical supply chain keeps pace with the interconnect demands of the 448Gbps era.
| APPROACH | BANDWIDTH | CROSSTALK | READINESS |
| Traditional PCB (optimized) | ~90–110 GHz | −40 dB | Available now with advanced materials |
| SLP (mSAP + Laser Microvia) | >150 GHz (no resonance) | < −50 dB | Most promising platform for 448Gbps |
The path to 448Gbps is clear: ultra-low-loss materials, aggressive via optimization, and SLP adoption will define the winners. The copper channel can still deliver — but only if we design it with the same rigor we apply to the optics on either end.